Multi-Level Analysis of On-Chip Optical Wireless Links

Fuschini, Franco; Barbiroli, Marina; Calò, Giovanna; Tralli, Velio; Bellanca, Gaetano; Zoli, Marco; Shafiei Dehkordi, Jinous; Nanni, Jacopo; Alam, Badrul; Petruzzelli, Vincenzo
January 2020
Applied Sciences (2076-3417);Jan2020, Vol. 10 Issue 1, p196
Academic Journal
Featured Application: Optical wireless communication on-chip may represent a breakthrough in the development of chip multi-core-processors, paving the way towards kilo-cores architectures. Beneficial fallout can be then envisaged in many technical fields, like augmented/virtual-reality, artificial-intelligence, automotive communications and data-centers for cloud-computing. Networks-on-chip are being regarded as a promising solution to meet the on-going requirement for higher and higher computation capacity. In view of future kilo-cores architectures, electrical wired connections are likely to become inefficient and alternative technologies are being widely investigated. Wireless communications on chip may be therefore leveraged to overcome the bottleneck of physical interconnections. This work deals with wireless networks-on-chip at optical frequencies, which can simplify the network layout and reduce the communication latency, easing the antenna on-chip integration process at the same time. On the other end, optical wireless communication on-chip can be limited by the heavy propagation losses and the possible cross-link interference. Assessment of the optical wireless network in terms of bit error probability and maximum communication range is here investigated through a multi-level approach. Manifold aspects, concurring to the final system performance, are simultaneously taken into account, like the antenna radiation properties, the data-rate of the core-to core communication, the geometrical and electromagnetic layout of the chip and the noise and interference level. Simulations results suggest that communication up to some hundreds of μm can be pursued provided that the antenna design and/or the target data-rate are carefully tailored to the actual layout of the chip.


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